Intel 8080 Core Architecture and Data Manipulation

Key Insight

The Intel 8080 microprocessor required three distinct power supply voltages: 5 volts (pin 20), -5 volts (pin 11), and 12 volts (pin 28), with pin 2 connected to ground. This was simplified in the later 8085 chip (1976). It required two synchronized 2 MHz clock inputs (phi 1 on pin 22 and phi 2 on pin 15), typically supplied by an Intel 8224 Clock Signal Generator chip using an 18 MHz quartz crystal. The 8080 used 16 address signals (A0-A15) to address up to 2^16, or 65536, bytes of memory. Data was read from and written to memory 8 bits at a time via eight bidirectional data signals (D0-D7). The remaining ten pins were control signals, such as RESET and a signal indicating a memory write operation.

The 8080 contained an 8-bit accumulator (A) and six general-purpose 8-bit registers: B, C, D, E, H, and L. Registers H and L could be treated as a 16-bit register pair (HL), with H as the high-order byte and L as the low-order byte, often used for memory addressing. A significant portion of the 8080's instruction set, 63 opcodes, was dedicated to the MOV (Move) instruction, enabling single-byte transfers between registers (e.g., MOV B,C) or between a register and a memory location specified by the HL pair (e.g., MOV B,[HL]). The MOV opcode uses a bit pattern (01dddsss) to encode destination and source registers or memory location.

The 8080 supported three main memory addressing methods: direct addressing, where the 16-bit address follows the instruction (e.g., LDA A,[aaaa]); indexed addressing, where the address is stored in a register pair like HL (e.g., MOV B,[HL]); and immediate addressing, used by the MVI (Move Immediate) instruction where the data byte immediately follows the opcode (e.g., MVI E,37h). Arithmetic instructions included ADD, ADC (Add with Carry), SUB, and SBB (Subtract with Borrow), where the accumulator typically served as one operand and the destination. Logical bitwise operations (AND, OR, XOR) and CMP (Compare) also existed, with CMP affecting flags without storing the result. Additional instructions like DAA (Decimal Adjust Accumulator) facilitated BCD arithmetic, CMA (Complement Accumulator) performed ones' complement, INR/DCR (Increment/Decrement) modified registers or memory by 1, and Rotate instructions (RLC, RRC, RAL, RAR) shifted accumulator bits, affecting the Carry flag.