Expanding the Automated Adder's Capabilities and Instruction Set

Key Insight

The initial automated adder suffered from several shortcomings: it could only perform addition, was limited to 8-bit numbers with results not exceeding 255, lacked a stop mechanism, and could not store results for later use. To address these issues, the machine was reconfigured to offer greater versatility. The display lightbulbs were removed, and the latch's output was connected to the RAM data input, enabling the storage of calculated sums directly back into the memory array for convenient examination.

A crucial architectural evolution involved introducing specific operation codes, or opcodes, to direct the machine's actions. These included 'Load' (10h) to transfer a byte from memory to the accumulator, 'Add' (20h) to sum a memory byte with the accumulator's contents, 'Store' (11h) to save the accumulator's value into memory, and 'Halt' (FFh) to stop operations. These opcodes, along with the data they manipulated, were initially stored in separate 'Code' and 'Data' RAM arrays, with corresponding addresses.

Further enhancements expanded the machine's arithmetic capabilities. A 'Subtract' operation (21h) was added, requiring data inversion and a carry input to the adder. To handle multi-byte numbers (e.g., 16-bit, 24-bit, 32-bit), a 1-bit 'Carry latch' was introduced. This latch saved the carry-out from an 8-bit addition, which then served as the carry-input for subsequent higher-order byte additions. New instructions like 'Add with Carry' (22h) and 'Subtract with Borrow' (23h) facilitated these multi-byte calculations, significantly expanding the machine's numerical processing scope.