Core Architecture and Basic Arithmetic Operations

Key Insight

The initial automated adder design employs 8-bit data paths connecting key components. A 16-bit counter supplies addresses for two RAM arrays. The Data RAM array's output feeds an 8-bit adder for 'Add' instructions. An 8-bit latch receives input from either the Data RAM (for 'Load' instructions) or the adder (for 'Add' instructions), necessitating a 2-to-1 selector. The latch's output cycles back to the adder and acts as the data input for the Data RAM during 'Store' instructions.

The underlying control signals, vital for coordinating component actions, are generated by various logic gates based on the Code RAM array's output. These signals include Clock and Clear inputs for the 16-bit counter and 8-bit latch, the Write input for the Data RAM array, and the Select input for the 2-to-1 selector. For example, the Select input must be 0 to select the Data RAM output for a 'Load' instruction, and the Data RAM's Write input must be 1 exclusively for a 'Store' instruction.

To expand its functionality, the circuit was enhanced to perform subtraction with minimal additional hardware. The operation codes were extended to include 'Subtract' (21h), alongside 'Load' (10h), 'Store' (11h), 'Add' (20h), and 'Halt' (FFh). For a 'Subtract' instruction, the data from the Data RAM array is inverted before reaching the adder, and the adder's carry input is set to 1. An example computation, adding 56h and 2Ah then subtracting 38h, yields a result of 48h.